OpSIS offers workshops aimed at getting participants up to speed on the modelling and design methodologies for silicon photonic devices and circuits. The workshops cover background theory of photonic devices (optical waveguides, directional couplers, resonators, fiber grating couplers, edge couplers, Mach Zehnder interferometers, modulators, detectors, etc), design considerations for fabrication using the OpSIS foundry service, and extensive hands-on tutorials for the modelling and design of passive and active photonic devices, mask layout, and design rule checking (DRC). The workshop also focuses on a specific process development kit (PDK) for the chosen fabrication foundry.
Workshops and Seminars
OpSIS Silicon Photonics Sub-System Design Workshop
June 17th-21st, 2013
Red Lion Hotel Portland – Convention Center
1021 Northeast Grand Avenue
Portland, OR 97232
We have worked out a discounted rate with the Red Lion hotel for our attendees.
Book at www.redlion.com/conventioncenter using the Group Code: OPSI0613
Standard Registration: $3,000 USD per person
Academic Registration: $1,500 USD per person (full-time university faculty or student)
To register please visit: http://opsisworkshop.eventbrite.com
Note: Registration closes June 10th
Engineers and scientists in the optoelectronic and semiconductor industry and anyone involved in research, manufacturing, or design of silicon photonic chips and/or complex optoelectronic systems.
This workshop will introduce you to silicon photonics and the OpSIS (Optoelectronic Systems Integration in Silicon) platform and foundry service – a breakthrough platform that holds huge promise for fabricating complex systems with affordable and reliable techniques, allowing the movement of information using light as well as electricity.
This workshop will be an in-depth, hands-on introduction to photonics design using OpSIS design kits. The objective is to train people to independently design photonic circuits, and interact successfully with OpSIS to tape-out their own chips using the OpSIS-IME process.
Workshop participants will design a silicon photonic test chip consisting of library components including edge and grating couplers, waveguides, directional couplers and Y branches, Mach-Zehnder thermo-optic switches, high-speed ring and travelling wave modulators, and high-speed detectors. In addition we will design an on-chip optical link.
This workshop targets the OpSIS-IME-004 or 005 tape-out dates.
- A non-disclosure agreement is required for access to the OpSIS-IME design kit. This will be sent to you after you register.
- Register and download Lumerical MODE, FDTD, DEVICE, and INTERCONNECT trials from http://www.lumerical.com.
- Please bring the license files you receive after registering with you to the workshop on a USB drive. These will be sent to you after you download their software.
- Prior to workshop, completion of the following Lumerical webinar tutorials:
- Workshop instruction
- Access to Mentor Graphics Pyxis and Calibre
- Software licenses for Lumerical’s FDTD Solutions, MODE Solutions, DEVICE and INTERCONNECT available via trial license
- Daily lunch
OFC/NFOEC Rump Session: Tuesday, March 19th from 7:30PM to 9:30PM
Silicon Photonics: Disruptive Technology or Research Curiosity?
Elite 1-3 Room in the Anaheim Marriot Hotel next to the Convention Center.
OpSIS Silicon Photonics Design Seminar: Thursday, March 21st from 2:00PM to 4:00PM OFC Show Floor, Hall A, Expo Theater III
The OpSIS MPW Foundry will be holding a 2-hour, silicon photonics design seminar at the OFC/NFOEC conference to present the OpSIS-IME and OpSIS-Luxtera design tools kits for designing and building silicon photonics devices.
The OpSIS-IME Multi-Project Wafer program will be presented by OpSIS Program Director, Michael Hochberg, who will speak about the OpSIS MPW program details, our latest photonic device developments, and the costs involved in developing and processing silicon photonics prototype chips from the OpSIS Institute and its partners Mentor Graphics, Mentor Pyxis, Calibre, and Lumerical software packages will be discussed.
The soon to be released OpSIS-Luxtera program will be discussed by Thierry Pinguet, Director of Semiconductor Process Development from Luxtera. The Luxtera process monolithically integrates CMOS transistor electronics with photonics on the same chip. Several videos of actual chip designs will be shown that demonstrate the proprietary Luxtera-developed design software tool kit in combination with Cadence design software. See www.Luxtera.com
When: Thursday, March 21st from 2:00PM to 4:00PM;
Where: OFC show floor, Hall A, Expo Theater III. Attendance is free.
OpSIS Silicon Photonics Workshop Open for Registration: February 18th-22nd
The Optoelectronic Systems Integration in Silicon (OpSIS) program run by the University of Delaware will be holding its second 5-day silicon photonics design course February 18-22nd.
This in-depth, hands-on workshop will introduce students to silicon photonics optical design techniques using several design software programs:
- OpSIS custom-developed Process Design Kit (PDK) including pre-designed devices
- Access to Mentor Graphics Pyxis and Calibre programs;
- Software licenses for Lumerical’s FDTD Solutions, MODE Solutions, DEVICE and INTERCONNECT;
The course objective will train students to be able to independently complete designs of photonic circuits, and interact with the OpSIS PDK to build their own chips using the OpSIS-IME process. Workshop participants will design a complete 10-20 Gb/s optical link consisting two chips. Each chip includes: an 8-channel WDM transmitter/receiver using thermally-tuned ring modulators; Ring demultiplexers and Germanium detectors; Fiber attachment using grating/edge-couplers to an external laser array source.
The OpSIS program is helping advance the silicon photonics field by bringing prototyping capability within reach of startups and academic research groups. OpSIS enables participants to design silicon photonics prototype chips by using the OpSIS-IME PDK with partner software and have them processed at the Singapore-based ASTAR IME fab at very low costs. Wafer mask set costs are shared across multiple users by using a Multi-Project Wafer (MPW) shuttle model which results in overall cost reductions of 50-100X over conventional techniques. The OpSIS program is open to all corporations, universities, labs and individuals.
Date: Feb. 18th – February 22nd, 2013; 9:00AM–5:00PM
Location: 1762 Technology Drive, Suite 227, San Jose, CA 95110 USA
Register early –space is limited! Credit cards accepted. http://opsis.eventbrite.com/
Workshop Description & CALPT Website
What to expect of introductory webinars and hands-on workshops:
Webinar (4 hours)
Introduction to silicon photonics and OpSIS, OpSIS-IME process description and device layout.
Hands-on Workshop (5 days)
University of Delaware, Newark Campus. Agenda includes introduction to silicon photonics and OpSIS, tutorials, demonstrations, lab tour, best practices and IME-based physical design.
HANDS-ON WORKSHOP SYLLABUS
- Introduction to optical and optoelectronic devices in silicon (1/2 day)
- Introduction to Process Development Kits (1/2 day); Best practices for design, layout, and testability
- IME-based physical design (Day 2); Mentor Graphics Pyxis, OpSIS library, scripting, auto-routing, DRC, tiling; system design
- Luxtera-based design (Day 3); Cadence, library elements, schematic driven layout (SDL), Physical verification (DRC, LVS, Tiling); schematic driven layout of a small optical system